The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. Conventionally, semiconductor devices are fabricated by patterning a sequence of patterned and un-patterned layers, and the features on successive patterned layers are spatially related to each other. During the fabrication, each patterned layer must be aligned with the previous patterned layers with a degree of precision. Pattern alignment techniques typically provide alignment marks for single-site alignment to achieve overall exposure field alignment. As technology nodes continue to decrease, it has been observed that such alignment techniques provide less than desirable alignment within the field.